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Preliminary Technical Data
Table 4. SPI Master Mode Timing (SPICPHA = 1) Parameters
ADE7566/ADE7569
Parameter
Description
Min
Typ
Max
Unit
t SL
t SH
t DAV
t DSU
t DHD
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK Edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
TBD
TBD
(SPIR + 1) × t CORE 1
(SPIR +1 ) × t CORE1
25
ns
ns
ns
ns
ns
t DF
t DR
t SR
t SF
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
5
5
5
5
12.5
12.5
12.5
12.5
ns
ns
ns
ns
1
t CORE depends on the clock divider or CD bits of the POWCON SFR, t CORE = 2 CD /4.096 MHz.
SCLK
(SPICPOL = 0)
t SH
t SL
SCLK
(SPICPOL = 1)
t SR
t SF
MOSI
t DAV
t DF
t DR
MSB
BITS 6–1
LSB
MISO
t DSU
MSB IN
t DHD
BITS 6–1
LSB IN
Figure 4. SPI Master Mode Timing (SPICPHA = 1)
Rev. PrA | Page 11 of 136
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